1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which has local and global data line pairs and a method of arranging a decoupling capacitor thereof.
2. Description of the Related Art
A decoupling capacitor of a semiconductor memory device is an elementary component used to filter noise which exists between power lines such as a first power voltage line and a second power voltage line.
In general, a decoupling capacitor of a conventional semiconductor memory device is arranged not on a memory cell array region but on an empty space of a peripheral circuit region. Therefore, a region on which a decoupling capacitor is arranged is limited, and in order to have effective noise filtering, a decoupling capacitor having a high capacitance should be arranged on the limited region.
Also, a decoupling capacitor of a conventional semiconductor memory device has a plurality of MOS capacitors, which are connected in parallel, between first and second power voltage lines.
FIG. 1 is a schematic view illustrating an arrangement of a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 includes a memory cell array 10, a column decoder 12, and decoupling capacitor blocks 14-1 and 14-2.
As shown in FIG. 1, the memory cell array 10 includes a plurality of sub memory cell array blocks SMCA that are arranged in vertical or transverse directions, sense amplifiers SA that are arranged on both left and right sides of a plurality of sub memory cell array blocks SMCA, and sub word line drivers SWD that are arranged above and below a plurality of sub memory cell array blocks SMCA. Conjunction regions CJ are arranged between the sub word line drivers SWD. A control signal generating circuit for controlling the sub word line driver SWD and a control signal generating circuit for controlling the sense amplifier SA are arranged on the conjunction region CJ. Data I/O lines 10 are arranged in a vertical direction, and first and second power voltage lines VCCA and VSSA, respectively, are alternately arranged in a transverse direction. Data I/O line pairs IO11, IO12 to IO(k−1)k,IOkk are arranged in a transverse direction above regions on which the sense amplifiers SA and the conjunction regions CJ are arranged.
A decoupling capacitor of the conventional semiconductor memory device described above is arranged on an empty region of the column decoder 12 and between the first power voltage line VCCA and the second power voltage line VSSA of the decoupling capacitor blocks 14-1 and 14-2. The first power voltage line VCCA is greater in level than the second power voltage line VSSA, and the decoupling capacitor includes MOS capacitors.
FIG. 2 is a schematic view illustrating the sense amplifier SA of the conventional semiconductor memory device of FIG. 1. The sense amplifier SA includes a PMOS sense amplifier PSA, a data I/O gate IOG, and an NMOS sense amplifier NSA.
The PMOS sense amplifier PSA includes PMOS transistors P1 and P2, which are connected between each of a plurality of bit line pairs BL1,BL1B to BLn,BLnB. The NMOS sense amplifier NSA includes NMOS transistors N1 and N2, which are connected between each of a plurality of bit line pairs BL1,BL1B to BLn,BLnB. The data I/O gate IOG includes NMOS transistors N3 and N4, which are connected between each of a plurality of bit line pairs BL1,BL1B to BLn,BLnB and between the data I/O line pair IO and IOB.
Operation of the sense amplifier SA is explained below.
The PMOS sense amplifier PSA is connected to the first power voltage line VCCA and amplifies data of a “low” level of a plurality of bit line pairs BL1,BL1B to BLn,BLnB to a first power voltage level when a first power voltage is supplied thereto. The NMOS sense amplifier NSA is connected to the second power voltage line VSSA and amplifies data of a “high” level of a plurality of bit line pairs BL1,BL1B to BLn,BLnB to a second power voltage level when a second power voltage is supplied thereto. The data I/O gate IOG is turned on in response to each of column selecting signals CSL1 to CSLn to transmit data between one of a plurality of bit line pairs BL1,BL1B to BLn,BLnB and the data I/O line pair IO,IOB.
The sense amplifiers of the semiconductor memory device of FIG. 1 have the same configuration as the sense amplifier of FIG. 2. Therefore, as shown in FIG. 2, there is no empty space which provides a region on which the decoupling capacitor could be arranged. That is, the decoupling capacitor cannot be arranged in the memory cell array of the conventional semiconductor memory device.
In the conventional semiconductor memory device, the sense amplifiers connected to a plurality of bit lines simultaneously operate at a point in time where the bit line is sensed, thereby generating noise. As a result, the level of the first power voltage falls transiently, and the level of the second power voltage rises transiently. The decoupling capacitor can mitigate a level variation of the first and second power voltages.
However, since the decoupling capacitors, which can mitigate a level variation of the first and second power voltages, are arranged only on a peripheral region of the memory cell array, the sense amplifiers arranged on a central portion of the memory cell array are delayed in amplifying the first and second power voltages, thereby deteriorating the operational performance of the semiconductor memory device.